1. Field of Invention
The present invention relates to the circuit and operating method of an asynchronous transmission receiver. More particularly, the present invention relates to the transmission convergence sublayer circuit and operating method of an asynchronous transmission receiver.
2. Description of Related Art
In a communication system, data is transferred from an emission system to a reception system through a transmission medium. The transmitted data is assembled together according to specified communication protocols in several layers. Similarly, the reception system processes the received data layer by layer according to the communication protocols. Among the communication protocols, the lowest layer unit is the physical layer. In asynchronous transfer mode, the physical layer is further divided into two units, namely, a physical medium and a transmission convergence sublayer.
FIG. 1 shows the data format of cell data processed by the transmission convergence sublayer at the transmission terminal working in the asynchronous transfer mode. The data format is decided by international telecommunication union (ITU) according to broadband integrated service digital network (B-ISDN) proposal ITU-T I.432. The proposed specification stipulates that the data format of a cell using an asynchronous transfer mode must have a size capable of accommodating 53 bytes. The 53 bytes include 5 bytes of header and 48 bytes of the so-called payload. The 5 bytes of header further comprises 4 bits of general flow control (GFC) code, 8 bits of virtual transmission path identification (VPI) code, 16 bits of virtual transmission channel identification (VCI), 3 bits of package type (PT) code, 1 bit of loss package classification (CLP) code and 8 bits of header error control (HEC) code.
To ensure correctness of header cell data at the receiving terminal, the first 32 bits in the header cell is applied to a cyclic redundancy check (CRC) polynomial X8+X2+X+1 to produce an 8-bit header cyclic redundancy code. FIG. 2A is a block showing a conventional method of using a header cyclic redundancy code generator at the emission terminal to produce header cyclic redundancy code. The circuit in FIG. 2A is capable of generating necessary header cyclic redundancy code for data error detection.
The upper layer unit generates transmission data according to an asynchronous transfer communication protocol. The transmission data at the transfer terminal of the transmission convergence sublayer is scrambled to produce the payload within the data cell according to a scrambling polynomial X43+1.
In general, the asynchronous transfer mode is structured upon a synchronized transmission system with a fixed bandwidth. When nothing is transmitted from an upper layer unit, the transmission convergence sublayer must generate an idle cell having special header and payload and the idle cell data must be transferred to a physical medium for transmission rate matching. The processing work required to be performed by the transmission convergence sublayer at the receiving terminal in an asynchronous transfer mode includes receiving a data stream and comparing the data stream with header cyclic redundancy code to find the header cell. Ultimately, data cells are correctly positioned and synchronously received. Once such synchronized state is reached, correctness of the header cell data in subsequently received data cells are checked and the payload within the data cell is descrambled. If the header cell is found to be correct and the data cell is not an idle cell, the header cyclic redundancy code in the header cell is removed. The data cell is rearranged to form a word and the word is written into a buffer. Finally, the word data is transferred to an upper layer for subsequent treatment.
FIG. 2B is a block diagram showing a conventional data cell synchronizing circuit for a receiver terminal operating in an asynchronous transfer mode. Reference is made to FIG. 2B for synchronizing reception of data cells in the transmission convergence sublayer by an asynchronous receiving terminal and the method of checking the correctness of header cells within the data cells received after synchrony.
In FIG. 2B, a modulo 2 adder 202, a D-type flip-flop 204 and a cyclic redundancy check arithmetic operation circuit 206 together form a long division circuit. The number to be divided is the first 40 bits of data in the data cell and the divisor is the polynomial X8+X2+X+1. If the result of calculation is correct, a decoder 208 decodes the computed value to obtain a cell synchronizing pulse. On the other hand, if the result of calculation is incorrect, 8 bits of data move in from the data cell to conduct a division. However, the earliest 8 bits of the previously divided 40 bit data must be corrected to eliminate any effect in the next round of division operation. The circuit comprising another modulo 2 adder 210, D-type flip-flop 214 and remainder arithmetic operation circuit 212 serve to eliminate the effect the 8 bit data has on the next round of division operation.
The function of the circuit in FIG. 2B is to operate on the received data stream. Through a comparison with the header cyclic redundancy code, the header cell is found. Hence, the data cells are received in synchrony. Furthermore, after data cell synchronization, header cyclic redundancy code comparison of subsequently received data cells continues.
However, to descramble the payload within a data cell, rearrange the data format from byte groups to word groups or double word groups and submit to buffer for processing by the upper layer unit, additional secondary circuit stages must be introduced. Hence, synchronized reception, header inspection, data descrambling and data format rearrangement must rely on the complicated integration of circuits such as the one shown in FIG. 2B and any additional secondary circuit stages. Consequently, data processing takes longer to complete.